Currently, conventional electronic device packaging methods are reaching their limits, as the demands for miniaturization and higher density of devices continue to increase. Generally, multi-chip packaging refers to an electronic packaging where multiple integrated circuits (ICs), semiconductor dies, or other discrete components are packaged onto a unifying substrate.
Generally, the substrate of a package comprises a plurality of metal layers separated by dielectric layers. Conductive vias are used to provide electrical connections between the metal layers. Typically, a metal via is formed on a metal pad deposited on a substrate layer using a laser drilling or an etching technique. The minimum size of the pad needs to be substantially greater than the size of the via to accommodate for misalignment. Standard packaging techniques, for example, provide 49 micron (μm) diameter, laser-drilled vias on large 77 μm diameter pads to accommodate for the ±14 μm misalignment.
Currently, via-pad structures are formed using registration of either laser drilling or a lithographic mask defining the via to existing fiducials on a pad layer of the substrate. However, due to shrinkage during curing of the dielectric layer deposited on the pad layer of the substrate and shifting the pad with respect to the fiducials, the via-to-pad registration is not preserved across the field of the substrate layer. The via-pad misalignment may cause device failures, decrease yield and increase manufacturing cost. Additionally, the large size of the pads, and the reduced via registration capability limit the density of metal lines and other components on the substrate.